Low power electronics for brain machine interface applications
Brain machine interfaces for the treatment of paralysis will require implantable devices that can record from hundreds of neural channels simultaneously. With existing techniques, this will require too much power consumption to run on conventional implantable batteries. This is currently limiting the speed of clinical translation, since devices will not be able to reuse existing implantable components. However, there is reason to believe that the current systems for digitizing and processing these signals are overdesigned. In the end, only a few bits per second actually needs to be transmitted to the end effector. We will examine reduced front end architectures that could dramatically lower the power consumption of the implant without suffering any measureable drop in signal quality.
$283,890 grant from the Craig Neilsen Foundation